Encoding:

Format:

PRECR_SRA[_R].PH.W 

PRECR_SRA.PH.W    rt, rs, sa

PRECR_SRA_R.PH.W   rt, rs, sa

Purpose:

Precision Reduce Two Integer Words to Halfwords after a Right Shift

Do an arithmetic right shift of two integer words with optional rounding, and then reduce the precision to halfwords.

Description:

rt = sign_extend((round(rt>>shift))15..0 || (round(rs>>shift))15..0)

The two right-most words in registers rs and rt are right shifted arithmetically by the specified shift amount sa to create interim results. The 16 least-significant bits of each interim result are then written to the corresponding elements of destination register rt.

In the rounding version of the instruction, a value of 1 is added at the most-significant discarded bit position after the shift is performed. The 16 least-significant bits of each interim result are then written to the corresponding elements of destination register rt.

The shift amount sa is interpreted as a five-bit unsigned integer taking values between 0 and 31.

The sign of the left-most halfword result is extended into the 32 most-significant bits of destination register rt.

This instruction does not write any bits of the ouflag field in the DSPControl register.

Restrictions:

No data-dependent exceptions are possible.

The operands must be a value in the specified format. If they are not, the results are UNPREDICTABLE and the values of the operand vectors become UNPREDICTABLE.

Operation:

PRECR_SRA.PH.W:
   if (sa4..0 = 0) then
      tempB15..0 = GPR[rt]15..0
      tempA15..0 = GPR[rs]15..0
   else
      tempB15..0 = ( (GPR[rt]31)sa || GPR[rt]31..sa )
      tempA15..0 = ( (GPR[rs]31)sa || GPR[rs]31..sa )
   endif
   GPR[rt]63..0 = (tempB15)32 || tempB15..0 || tempA15..0
PRECR_SRA_R.PH.W:
   if (sa4..0 = 0) then
      tempB16..0 = ( GPR[rt]15..0 || 0 )
      tempA16..0 = ( GPR[rs]15..0 || 0 )
   else
      tempB32..0 = ( (GPR[rt]31)sa || GPR[rt]31..sa-1 ) + 1
      tempA32..0 = ( (GPR[rs]31)sa || GPR[rs]31..sa-1 ) + 1
   endif
   GPR[rt]63..0 = (tempB16)32 || tempB16..1 || tempA16..1

Exceptions:

Reserved Instruction, DSP Disabled